The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
Photoresist materials are coated onto the surface of a wafer by dispensing a photoresist fluid typically on the center of the wafer as the wafer rotates at high speeds within a stationary bowl or coater cup. The coater cup catches excess fluids and particles ejected from the rotating wafer during application of the photoresist. The photoresist fluid dispensed onto the center of the wafer is spread outwardly toward the edges of the wafer by surface tension generated by the centrifugal force of the rotating wafer. This facilitates uniform application of the liquid photoresist on the entire surface of the wafer.
During the photolithography step of semiconductor production, light energy is applied through a reticle mask onto the photoresist material previously deposited on the wafer to define circuit patterns which will be etched in a subsequent processing step to define the circuits on the wafer. A reticle is a transparent plate patterned with a circuit image to be formed in the photoresist coating on the wafer. A reticle contains the circuit pattern image for only a few of the die on a wafer, such as four die, for example, and thus, must be stepped and repeated across the entire surface of the wafer. In contrast, a photomask, or mask, includes the circuit pattern image for all of the die on a wafer and requires only one exposure to transfer the circuit pattern image for all of the dies to the wafer.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner.
A typical method of forming a circuit pattern on a wafer includes introducing the wafer into the automated track system and then spin-coating a photoresist layer onto the wafer. The photoresist is next cured by conducting a soft bake process. After it is cooled, the wafer is placed in an exposure apparatus, such as a stepper, which aligns the wafer with an array of die patterns etched on the typically chrome-coated quartz reticle. When properly aligned and focused, the stepper exposes a small area of the wafer, then shifts or “steps” to the next field and repeats the process until the entire wafer surface has been exposed to the die patterns on the reticle. The photoresist is exposed to light through the reticle in the circuit image pattern. Exposure of the photoresist to this image pattern cross-links and hardens the resist in the circuit pattern. After the aligning and exposing step, the wafer is exposed to post-exposure baking and then is developed and hard-baked to develop the photoresist pattern.
The circuit pattern defined by the developed and hardened photoresist is next transferred to the underlying metal conductive layer using a metal etching process, in which metal over the entire surface of the wafer and not covered by the cross-linked photoresist is etched away from the wafer with the metal under the cross-linked photoresist that defines the circuit pattern protected from the etchant. As a result, a well-defined pattern of metallic microelectronic circuits which closely approximates the cross-linked photoresist circuit pattern remains in the metal layer.
Spin coating of photoresist on wafers, as well as the other steps in the photolithographty process, is typically carried out in an automated coater/developer track system using wafer handling equipment which transport the wafers between the various photolithography operation stations, such as vapor prime resist spin coat, develop, baking and chilling stations. Robotic handling of the wafers minimizes particle generation and wafer damage. Automated wafer tracks enable various processing operations to be carried out simultaneously. Two types of automated track systems widely used in the industry are the TEL (Tokyo Electron Limited) track and the SVG (Silicon Valley Group) track.
At the hard bake step of photolithography, a wafer transfer robot transfers the wafer onto a bake plate, which heats the wafer to a temperature of typically about 120–140 degrees C. for positive resists. The hard bake step evaporates the remaining photoresist solvent and improves adhesion of the resist to the wafer surface. The hard bake step stabilizes the resist following etch or implant processing. Both the bake plate target temperature and proper positioning of the wafer on the bake plate are critical for uniform thermal transmission from the bake plate to the wafer. Proper positioning of a wafer on a bake plate is particularly important for 0.13 μm technology applications and for wafers having a 12″ diameter.
To ensure proper positioning of the wafer on the bake plate, the transfer position of the wafer onto the bake plate must typically be verified by a process engineer at each PM cycle. During processing, however, particles can fall off of wafers onto the bake plate and render abnormal the positioning of the wafer on the bake plate. Such abnormal positioning can be difficult to verify and is frequently manifested by a broken wafer or abnormal CD bias or uniformity in the devices fabricated on the wafer. Accordingly, a real-time wafer position-detecting system and method is needed to precisely indicate whether a wafer is properly positioned on a bake plate prior to commencement of a bake process in semiconductor photolithography.
An object of the present invention is to provide a novel real-time wafer position-detecting system which can be used to determine whether a wafer is properly positioned on a bake plate.
Another object of the present invention is to provide a novel wafer position-detecting system which is applicable to photolithography and other semiconductor processes.
Still another object of the present invention is to provide a novel temperature-sensing wafer position detection system.
Yet another object of the present invention is to provide a novel wafer position detection system which includes a bake plate and a temperature-sensing apparatus which engages the bake plate and measures the change in temperature (ΔT) of the bake plate over a specified time interval to determine whether the wafer is properly or improperly positioned on the support.
A still further object of the present invention is to provide a real-time wafer position-detecting method which includes setting a bake plate at a temperature set point, transferring a wafer onto the bake plate, measuring the change in temperature (ΔT) of the bake plate over a specified time interval, determining whether the wafer is improperly positioned on the wafer support based on the change in temperature, and aborting a bake process in the event that the wafer is improperly positioned on the bake plate.